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not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs document id# 080449 date: jun 18, 2002 rev: b version: 1 distribution: public document le7926 subscriber line interface circuit the le7926 subscriber line interface circuit implements the basic telephone line interface functions, and enables the design of low power, high performance, pots line interface cards. distinctive characteristics ideal for high-density, low-power linecard applications control states: active, reverse polarity, tip open, ringing, standby, and open circuit low standby power (45 mw) ?16 v to ?58 v battery operation on-hook transmission two-wire impedance set by single external impedance programmable constant-current feed low overhead voltage (6 v) programmable loop-detect threshold ground-start detector programmable ring-trip detect threshold no ?5 v supply required current gain = 500 three on-chip relay drivers and relay snubbers, one ringing and two general purpose tip open state for ground-start lines block diagram controller two-wire interface signal transmission input decoder and control off-hook detector power-feed ryout2 ryout1 relay driver relay driver relay driver ring-trip detector d1 d2 c1 c2 c3 det vtx rsn rd rdc cas vdc vcc vbref agnd a(tip) hpa hpb b(ring) vs vbat2 da db vbat1 bgnd ringout
not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs 2 le7926 data sheet ordering information standard products legerity standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the elements below. le7926* v c temperature range c = commercial (0c to +70c)* package type device number/description le7926 subscriber line interface circuit ?1 performance grade ?1 52 db longitudinal balance, polarity reversal ?2 63 db longitudinal balance, polarity reversal ?3 52 db longitudinal balance, no polarity reversal ?4 63 db longitudinal balance, no polarity reversal v = 44-pin thin plastic quad flat pack (pqt044) *legerity reserves the right to fulfill all orders for this device with parts mark ed with the "am" part number prefix, until su ch time as all inventory bearing this mark has been depleted. it should be noted that parts marked with either the "am" or the "le" part number prefix are equivalent devices in terms of form, fit, and function. the only difference between the two is in the pa rt number prefix appearing on the topside mark. valid combinations valid combinations le7926* ?1 ?2 ?3 ?4 vc valid combinations list configurations planned to be supported in volume for this device. consult the local legerity sales of fice to confirm availabil- ity of specific valid combinations, to check on newly released combinations.
not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs le7926 data sheet 3 connection diagrams top view hpa 1 2 3 4 5 6 7 8 9 33 32 31 30 29 28 27 26 25 42 41 40 39 38 37 36 vcc vbat2 n/c bgnd n/c b(ring) da rd vtx n/c n/c n/c le7926vc ryout1 vs n/c n/c n/c ryout2 vbat1 d1 d2 a(tip) n/c hpb 43 n/c 44 ringout 35 n/c 34 db 14 15 16 17 18 19 20 13 12 det 21 22 c3 c2 n/c n/c cas vdc rdc agnd n/c rsn 24 n/c 23 vbref 10 n/c 11 c1 notes: 1. pin 1 is marked for orientation. 2. n/c = no connect 3. rsvd = reserved. do not connect to this pin.
not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs 4 le7926 data sheet pin descriptions pin name type description agnd gnd analog and digital ground. a(tip) output output of a(tip) power amplifier. bgnd gnd battery (power) ground. b(ring) output output of b(ring) power amplifier. c3?c1 input slic control pins. c3 is msb and c1 is lsb. cas capacitor anti-saturation pin for capacitor to filter reference voltage when operating in anti- saturation region. d2?d1 input relay driver control. d1 and d2 control the relay drivers ryout1 and ryout2. logic low on d1 activates the ryout1 relay driver. logic low on d2 activates the ryout2 relay driver. da input negative input to ring-trip comparator. db input positive input to ring-trip comparator. det output switchhook detector. a logic low indicates that selected condition is detected. the detect condition is selected by the logic inpu ts (c3?c1). the output is open-collector with a built-in 15 k ? pull-up resistor. hpa capacitor a (tip) side of high-pass filter capacitor. hpb capacitor b (ring) side of high-pass filter capacitor. n/c ? no connect. this pin is not internally connected. rd resistor detector threshold set and filter pin. rdc resistor connection point for the dc feed current pr ogramming network. the other end of the network connects to the receiver summing node (rsn). ringout output ring relay driver. open-collector driv er with emitter internally connected to bgnd. rsn input receive summing node. the metallic current (both ac and dc) between a(tip) and b(ring) is equal to 500 times the current into this pin. the networks which program receive gain, two-wire impedance, and feed resistance all connect to this node. ryout1 output relay/switch driver. open-collector driver with emitter internally connected to bgnd. ryout2 output relay/switch driver. open-collector driver with emitter internally connected to bgnd. vbat1 battery battery supply and connection to substrate. when on hook, switcher should not be in use. current draw is from vbat1 vbat2 battery battery supply for output amplifiers. vbref ? this is a legerity reserved pin and must always be connected to the vbat pin. vcc power supply +5 v power supply. vdc output output that is proportional to the line voltage: vdc = | v a ?v b | / 20. vs output output that is equal to vreg min + 2.4 v (total overhead needed is 6 v). the output can be used as a control input to an external switching regulator. th e switching regulator output must be set to vs ?2.4 v (or more n egative) in order to guarantee performance of the slic. vtx output transmit audio. this output is a 0.50 gain version of the a(tip) and b(ring) metallic voltage. vtx also sources the two-wire input impedance programming network.
not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs le7926 data sheet 5 absolute maximum ratings storage temperature ........... .............. ?55c to +150c v cc with respect to agnd ................. ?0.4 v to +7.0 v v bat1 , v bat2 with respect to agnd: continuous..................................... +0.4 v to ?70 v 10 ms ............................................. +0.4 v to ?75 v bgnd with respect to agnd ................... +3 v to ?3 v a(tip) or b(ring) to bgnd: continuous ......................................... v bat to +1 v 10 ms (f = 0.1 hz) ............................. ?70 v to +5 v 1 s (f = 0.1 hz) ................................ ?80 v to +8 v 250 ns (f = 0.1 hz) .......................... ?90 v to +12 v current from a(tip) or b( ring).....................150 ma ringout/ryout1,2 current............................50 ma ringout/ryout1,2 voltage .............. bgnd to +7 v ringout/ryout1,2 transient .......... bgnd to +10 v da and db inputs voltage on ring-trip inputs ..................... v bat to 0 v current into ring-trip in puts ......................... 10 ma c3?c1 and d2?d1 input voltage .........................?0.4 v to v cc + 0.4 v maximum power dissipation, continuous, t a = 70c, no heat sink (see note) in 44-pin tqfp package................................1.4 w thermal data: ............................................................... . ja in 44-pin tqfp package....................... 52 c/w typ esd immunity/pin (hbm) ..................................1500 v note: thermal limiting circuitry on-chip will shut down the cir- cuit at a junction temperature of about 165 c. the device should never see this temperat ure and operation above 145c junction temperature may degrade device reliability. stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. operating ranges commercial (c) devices ambient temperature ............ .................0c to +70c* v cc .....................................................4.75 v to 5.25 v v bat1 , v bat2 .........................................?15 v to ?58 v agnd...................................................................... 0 v bgnd with respect to agnd ................................... ?100 mv to +100 mv load resistance on vtx to ground .............. 20 k ? min *the operating ranges define those limits between which the functionality of the device is guaranteed. * legerity guarantees the perfor mance of this device over commercial (0 to 70 c) and industrial (-40 to 85 c) temperature ranges by conductin g electrical characterization over each range and by conducting a production test with single insertion coupled to periodic sampling. these characterization and test procedures comply with section 4.6.2 of bellcore tr-tsy-000 357 component reliability assurance requirements for telecommunications equipment.
not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs 6 le7926 data sheet electrical characteristics description test conditions (see note 1) min typ max unit note transmission performance 2-wire return loss 200 hz to 3.4 khz 26 db 1, 4 analog output (vtx) impedance 1 20 ? 4 analog (vtx) output offset voltage ?50 +50 mv overload level, 2-wire active state 2.5 vpk 2a overload level on hook, r lac = 600 ? 0.77 vrms 2b thd, total harmonic distortion 0 dbm +7 dbm ?64 ?55 ?50 ?40 db 5 thd, on hook 0 dbm, r lac = 600 ? ?36 longitudinal capability (see test circuit d) longitudinal to metallic l-t, l-4 200 hz to 1 khz longitudinal to metallic l-t, l-4 1 khz to 3.4 khz normal polarity 0c to +70c -2,-4 -40c to +85c -2,-4 0c to +70c -1,-3 -40c to +85c -1,-3 reverse polarity -40c to +85c -2 0c to +70c -1 -40c to +85c -1 63 58 52 50 54 52 50 db 4 4 4 4 normal polarity 0c to +70c -2,-4 -40c to +85c -2,-4 0c to +70c -1,-3 -40c to +85c -1,-3 reverse polarity -40c to +85c -2 0c to +70c -1 -40c to +85c -1 58 53 52 50 53 52 50 4 4 4 4 longitudinal signal generation 4-l 200 hz to 3.4 khz 40 longitudinal current per pin (a or b) active state 17 27 marms 8 longitudinal impedance at a or b 0 to 100 hz 25 ? /pin 4 idle channel noise c-message weighted noise r l = 600 ? 0c to +70c r l = 600 ? ?40c to +85c 7+10 +12 dbrnc 4 psophometric weighted noise r l = 600 ? 0c to +70c r l = 600 ? ?40c to +85c ?83 ?80 ?78 dbmp insertion loss and balance return signal (see test circuits a and b) gain accuracy 4- to 2-wire 0 dbm, 1 khz ?0.20 0 +0.20 db 3 gain accuracy 2- to 4-wire, 4- to 4-wire 0 dbm, 1 khz ?6.22 ?6.02 ?5.82 3 gain accuracy, 4- to 2-wire on hook ?0.35 +0.35 3,4 gain accuracy, 2- to 4-wire, 4- to 4-wire on hook ?6.37 ?6.02 ?5.67 gain accuracy over frequency 300 to 3.4 khz relative to 1 khz ?0.15 +0.15 3 gain tracking +3 dbm to ?55 dbm relative to 0 dbm ?0.15 +0.15 3,4 gain tracking on hook 0 dbm to ?37 dbm +3 dbm to 0 dbm ?0.15 ?0.35 +0.15 +0.35 3,4 group delay 0 dbm, 1 khz 4 s 4, 7
not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs le7926 data sheet 7 electrical characteristics (continued) description test conditions (see note 1) min typ max unit note line characteristics i l , short loops, active state r ldc = 600 ? 22.5 24.5 26.5 ma i l , long loops, active state r ldc = 2010 ? , vbat = ?50 v 20 22.5 i l , accuracy, standby state 16 constant-current region 18 30 i l lim active, a and b to ground 75 120 ma vdc accuracy vdc = |vab| /20 ri = 300 to 1500 ? 0.053 0.055 0.057 9 vab, open circuit voltage v bat = v bat1 , v bat2 = ?50 v 42.75 44 v i a , leakage, tip open state r l = 0 100 a i b , current, tip open state b to gnd 15 30 56 ma v a , active ra to bat = 7 k ? , rb to gnd = 100 ? ?7.5 ?5 v 4 vs, act/nor il = 25 ma v bat = vs ?2.4 v vb?0.5 vb?1.1 vb?1.7 v vs, pol?rev il = 25 ma va?0.5 va?1.1 va?1.7 vs, max load ?20 100 a4 power supply rejection ratio v cc 50 hz to 3.4 khz (v ripple = 100 mvrms) 30 40 db 5 v bat 50 hz to 3.4 khz off-hook constant current (v ripple = 500 mvpp) 28 50 effective internal resistance cas pin to v bat 85 170 255 k ? 4 power dissipation on hook, standby state 45 60 mw on hook, active state 130 170 off hook, standby state r l = 600 ? 860 1200 off hook, active state r l = 600 ?, v bat = ? (|vab| + 6.5 v) 230 320 supply currents i cc , on-hook v cc supply current standby state active state 2.3 4.25 3.2 6.0 ma i bat , on-hook v bat supply current standby state active state 0.65 2.0 0.9 3.0 rfi rejection rfi rejection 100 khz to 30 mh z, (see figure f) 1.0 mvrms 4 receive summing node (rsn) rsn dc voltage i rsn = 0 ma 0 v 4 rsn impedance 200 hz to 3.4 khz 10 20 ? logic inputs (c3?c1 and d2?d1) v ih , input high voltage (except c3) 2.0 v v ih , c3 2.5 v il , input low voltage 0.8 i ih , input high current ?75 40 a i il , input low current ?400 logic output (det ) v ol , output low voltage i out = 0.3 ma, 15 k ? to v cc 0.40 v v oh , output high voltage i out = ?0.1 ma, 15 k ? to v cc 2.4 i l bat 3 v ? r l 400 + ------------------------------ -t a 25 c = =
not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs 8 le7926 data sheet electrical character istics (continued) relay driver schematics description test conditions (see note 1) min typ max unit note ring-trip detector input (da, db) bias current ?500 ?50 na offset voltage source resistance = 2 m ? ?50 0 +50 mv 6 loop detector on threshold r d = 35.4 k ? 9.4 11.7 14.0 ma off threshold r d = 35.4 k ? 8.8 10.4 12.0 hysteresis r d = 35.4 k ? 1.3 igk, ground-key detector threshold r l from bx to gnd active, standby, and tip open 5913ma relay driver output (r ingout, ryout1, ryout2) on voltage i ol = 40 ma +0.3 +0.7 v off leakage v oh = +5 v 100 a zener breakover i z = 100 a 6 7.2 v zener on voltage i z = 30 ma 8 ringout bgnd ryout1, ryout2 bgnd
not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs le7926 data sheet 9 notes: 1. unless otherwise noted, test conditions are vbat1 = vbat2 = ?52 v, v cc = +5 v, r l = 600 ? , r dc1 = r dc2 = 13.02k, r d = 35.4 k ? , no fuse resistors, c hp = 0.22 f, c dc = 0.33 f, c cas = 0.33 f, d1 = 1n400x, two-wire ac input impedance is a 600 ? resistance synthesized by the programming network shown below. 2. a. overload level is defined when thd = 1%. b. overload level is defined when thd = 1.5%. 3. balance return signal is the signal generated at v tx by v rx . this specification assumes that the two-wire, ac-load impedance matches the programmed impedance. 4. not tested in production. this parameter is guarant eed by characterization or correlation to other tests. 5. this parameter is tested at 1 khz in production. performanc e at other frequencies is g uaranteed by characterization. 6. tested with 0 ? source impedance. 2 m ? is specified for system design only. 7. group delay can be greatly reduced by using a z t network such as that shown in note 1. the network reduces the group delay to less than 2 s and increases 2wrl. the effect of group delay on linecard performance also may be compensated for by synthesizing complex impedance with the qslac? or dslac? device. 8. minimum current level guaranteed not to cause a false loop detect. 9. v dc /v ab table 1. slic decoding state c3 c2 c1 two-wire status det output 0 0 0 0 reserved x 1 0 0 1 reserved x 2 0 1 0 active polarity reversal loop detector 3 0 1 1 tip open ground key* 4 1 0 0 open circuit ring trip 5 1 0 1 ringing ring trip 6 1 1 0 active loop detector 7 1 1 1 standby loop detector *ground key selection in tip open is automatic. if longitudinal current is greater than 9 ma in active, standby, or tip open, the det will go low. therefore, if in active or standby, det may be an indication of off hook, ground key, or both. r rx = 150 k ? r t1 = 75 k ? vtx rsn v rx r t2 = 75 k ? c t1 = 120 pf
not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs 10 le7926 data sheet table 2. user-programmable components z t is connected between the vtx and rsn pins. the fuse resistors are r f , and z 2win is the desired 2-wire ac input impedance. when computing z t , the internal current amplifier pole and any external stray capacitance between vtx and rsn must be taken into account. z rx is connected from vrx to rsn. z t is defined above, and g 42l is the desired receive gain. r dc1 , r dc2 , and c dc form the network connected to the r dc pin. r dc1 and r dc2 are approximately equal. i loop is the desired loop current in the constant-current region. r d and c d form the network connected from r d to agnd/ dgnd and i t is the threshold current between on hook and off hook. c cas is the regulator filter capacitor and f c is the desired filter cut-off frequency. standby loop current (resistive region). z t 250 z 2win 2 r f ? () = z rx z l g 42l ------------ ? 500 z t z t 250 z l 2 r f + () + --------------------------------------------------- - = r dc1 r dc2 625 i loop --------------- = + c dc 1.5 ms r dc1 r dc2 + r dc1 r dc2 ? ---------------------------------- ? = rd on 390 i t --------- - rd off 355 i t --------- - c d 0.5 ms r d ---------------- - = , = , = c cas 1 3.4 10 5 f c ? ------------------------------ - = i standby v bat 3v ? 400 ? r l + --------------------------------- - =
not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs le7926 data sheet 11 a. load line (typical) notes: 1. constant current region: 2. battery tracking anti-sat (off hook): a) b) 3. battery tracking anti-sat (on hook): a) b) v ab i l r l ' 625 r dc ----------- - r l ' where r l ' r l 2 r f + = , = = v ab 41.6 v v ab = |v bat | -2.0 -i l (r dc /138) v ab 41.6 v v ab = .8|v bat | + 6.73 - i l (r dc /172) v ab 41.6 v v ab = |v bat | -5.3 - i l (r dc /138) v ab 41.6 v v ab = .8|v bat | + 4.08 - i l (r dc /172) 0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 v ab il (ma) dc characteristics
not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs 12 le7926 data sheet dc feed characteristics (continued) a (tip) b (ring) i l rsn rdc r dc1 r dc2 c dc slic r l b. feed programming feed current programmed by r dc1 and r dc2 figure 1. dc feed characteristics
not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs le7926 data sheet 13 test circuits r t r rx v ab v l r l 2 i l2-4 = 20 log (v tx / v ab ) a. two- to four-wire insertion loss a(tip) b(ring) agnd vtx rsn slic r l 2 r t v ab a(tip) b(ring) agnd vtx rsn slic r l r rx v rx i l4-2 = 20 log (v ab / v rx ) brs = 20 log (v tx / v rx ) b. four- to two-wire insertion loss and balance return signal r t r rx r l 2 r l 2 v rx s1 c s2 v l v l a(tip) b(ring) agnd vtx rsn slic 1 << r l l-4 long. bal. = 20 log (v tx / v l ) l-t long. bal. = 20 log (v ab / v l ) 4-l long. sig. gen. = 20 log (v l / v rx ) c. longitudinal balance v ab s2 open, s1 closed s2 closed, s1 open c
not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs 14 le7926 data sheet test circuits (continued) d. two-wire return loss test circuit r r return loss = ?20 log (2 v m / v s ) z d : the desired impedance; e.g., the characteristic impedance of the line v m z in v s a(tip) b(ring) agnd vtx r sn slic r t2 r rx c t1 r t1 z d e. rfi test circuit 50 ? l 1 200 ? 200 ? c 1 c 2 b hf gen vtx a l 2 cax 33 nf cbx 33 nf rf 1 rf 2 50 ? 50 ? 1.5 vrms 80% amplitude modulated 100 khz to 30 mhz slic under test
not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs le7926 data sheet 15 f. le7926 test circuit vcc r d rd vtx agnd rsn r rx r dc2 r dc1 c dc r t rdc c2 c1 +5 v vbat1 det d 1 bgnd ringout hpb c hp hpa db da a(tip) b(ring) cas c cas regulator 2.2 nf 2.2 nf v tx v rx a(tip) b(ring) ryout1 vbat2 ryout2 c3 d1 vbref battery ground analog ground d2 or bat vdc vs
not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs 16 le7926 data sheet application circuit f. le7926 application circuit vcc r d rd vtx agnd rsn r rx r dc2 c dc r tx1 rdc c2 c1 +5 v vbat1 det d 1 bgnd ringout hpb c hp hpa db da a(tip) b(ring) cas c cas regulator r f v tx v rx a(tip) b(ring) ryout1 vbat2 ryout2 c3 d1 vbref battery ground d2 or bat vdc vs 2.2 nf r f 2.2 nf r tx2 c tx c d r dc1 analog ground
not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs le7926 data sheet 17 physical dimension pqt044 bsc is an ansi standard for basic centering. dimensions ar e measured in millimeters. dwg rev. as; 08/00 tqfp 044 tqfp 044
not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs 18 le7926 data sheet revision summary revision a to revision a2 ? updated the pin description table to correct inconsistencies. ? the physical dimension (pqt044) was added to the physical dimension section. ? added the connection diagram on page 3. revision a2 to revision a3 ? changed 8 v to 6 v in the disti nctive characteristics section. ? added the 32-pin plcc information to the ordering information and absolute maximum ratings sections and added the connection diagram. ? in the electrical characteristics table: ? updated the information in the line characteristics section on the long loops row and the vdc accuracy row. ? deleted the disconnect state information in the power dissipation and supp ly currents sections. revision a3 to revision b ? updated opn (ordering part number) throughout document. ? replaced obsolete sale s office listing page. ? updated physical dimensions drawings. ? absolute maximum ratings: notes updated to standard. ? operating ranges: temperature statement updated to standard.
the contents of this document are provided in connection with legerity, inc. products. legerity makes no representations or war ranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time with out notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. except as set forth in legerity's standard te rms and conditions of sale, legerity assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. legerity's products are not designed, intend ed, authorized or warranted for use as co mponents in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of legerity's product could create a situation where personal injury, death, or severe property or environmental damage may occur. legerity reserves the right to discontinue or make changes to its products at any time without notice. ? 2002 legerity, inc. all rights reserved. trademarks legerity, the legerity logo and combinations thereof, and qslac, dslac, are trademarks of legerity, inc. other product names used in this publicati on are for identification purposes only and ma y be trademarks of their respective com panies.

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